CAN-LIN SBC Registers Settings

Settings for registers of CAN-LIN SBC Click driver. More...

Macros
#define	CANLINSBC_DMCR_RSTEN   0x20
	CAN-LIN SBC Device Mode Control Register (DMCR) setting.
#define	CANLINSBC_DMCR_VCCOVSD   0x10
#define	CANLINSBC_DMCR_SLPVCCUC   0x08
#define	CANLINSBC_DMCR_DOPM_SLEEP_MODE   0x01
#define	CANLINSBC_DMCR_DOPM_STANDBY_MODE   0x04
#define	CANLINSBC_DMCR_DOPM_NORMAL_MODE   0x07
#define	CANLINSBC_DMCR_DOPM_MASK   0x07
#define	CANLINSBC_TRXCR_CFDPE   0x40
	CAN-LIN SBC CAN Transceiver Control Register (TRXCR) setting.
#define	CANLINSBC_TRXCR_PNCFOK   0x20
#define	CANLINSBC_TRXCR_CPNE   0x10
#define	CANLINSBC_TRXCR_COMP_STANDBY_MODE   0x00
#define	CANLINSBC_TRXCR_COMP_NORMAL_MODE   0x01
#define	CANLINSBC_TRXCR_COMP_SILENT_MODE   0x03
#define	CANLINSBC_TRXCR_COMP_MASK   0x03
#define	CANLINSBC_WDCR1_WDC_OFF_MODE   0x20
	CAN-LIN SBC Watchdog Configuration Register 1 (WDCR1) setting.
#define	CANLINSBC_WDCR1_WDC_TIME_OUT_MODE   0x40
#define	CANLINSBC_WDCR1_WDC_WINDOW_MODE   0x80
#define	CANLINSBC_WDCR1_WDC_MASK   0xE0
#define	CANLINSBC_WDCR1_WDPRE_FACTOR_1   0x00
#define	CANLINSBC_WDCR1_WDPRE_FACTOR_1_5   0x08
#define	CANLINSBC_WDCR1_WDPRE_FACTOR_2_5   0x10
#define	CANLINSBC_WDCR1_WDPRE_FACTOR_3_5   0x18
#define	CANLINSBC_WDCR1_WDPRE_MASK   0x18
#define	CANLINSBC_WDCR1_WDLSP   0x04
#define	CANLINSBC_WDCR1_WDLW   0x02
#define	CANLINSBC_WDTRIG_RESET   0x55
	CAN-LIN SBC Watchdog Trigger Register (WDTRIG) setting.
#define	CANLINSBC_DEVICE_ID   0x86
	CAN-LIN SBC device ID setting.
#define	CANLINSBC_SET_DATA_SAMPLE_EDGE   SET_SPI_DATA_SAMPLE_EDGE
	Data sample selection.
#define	CANLINSBC_SET_DATA_SAMPLE_MIDDLE   SET_SPI_DATA_SAMPLE_MIDDLE
#define	CANLINSBC_TX_DRV_BUFFER_SIZE   100
	CAN-LIN SBC driver buffer size.
#define	CANLINSBC_RX_DRV_BUFFER_SIZE   300

Detailed Description

Settings for registers of CAN-LIN SBC Click driver.

Macro Definition Documentation

CANLINSBC_DEVICE_ID

#define CANLINSBC_DEVICE_ID   0x86

CAN-LIN SBC device ID setting.

Specified setting for device ID of CAN-LIN SBC Click driver.

CANLINSBC_DMCR_DOPM_MASK

#define CANLINSBC_DMCR_DOPM_MASK   0x07

CANLINSBC_DMCR_DOPM_NORMAL_MODE

#define CANLINSBC_DMCR_DOPM_NORMAL_MODE   0x07

CANLINSBC_DMCR_DOPM_SLEEP_MODE

#define CANLINSBC_DMCR_DOPM_SLEEP_MODE   0x01

CANLINSBC_DMCR_DOPM_STANDBY_MODE

#define CANLINSBC_DMCR_DOPM_STANDBY_MODE   0x04

CANLINSBC_DMCR_RSTEN

#define CANLINSBC_DMCR_RSTEN   0x20

CAN-LIN SBC Device Mode Control Register (DMCR) setting.

Specified setting for Device Mode Control Register (DMCR) of CAN-LIN SBC Click driver.

CANLINSBC_DMCR_SLPVCCUC

#define CANLINSBC_DMCR_SLPVCCUC   0x08

CANLINSBC_DMCR_VCCOVSD

#define CANLINSBC_DMCR_VCCOVSD   0x10

CANLINSBC_RX_DRV_BUFFER_SIZE

#define CANLINSBC_RX_DRV_BUFFER_SIZE   300

CANLINSBC_SET_DATA_SAMPLE_EDGE

#define CANLINSBC_SET_DATA_SAMPLE_EDGE   SET_SPI_DATA_SAMPLE_EDGE

Data sample selection.

This macro sets data samples for SPI modules.

Note

Available only on Microchip PIC family devices. This macro will set data sampling for all SPI modules on MCU. Can be overwritten with canlinsbc_init which will set SET_SPI_DATA_SAMPLE_MIDDLE by default on the mapped mikrobus.

CANLINSBC_SET_DATA_SAMPLE_MIDDLE

#define CANLINSBC_SET_DATA_SAMPLE_MIDDLE   SET_SPI_DATA_SAMPLE_MIDDLE

CANLINSBC_TRXCR_CFDPE

#define CANLINSBC_TRXCR_CFDPE   0x40

CAN-LIN SBC CAN Transceiver Control Register (TRXCR) setting.

Specified setting for CAN Transceiver Control Register (TRXCR) of CAN-LIN SBC Click driver.

CANLINSBC_TRXCR_COMP_MASK

#define CANLINSBC_TRXCR_COMP_MASK   0x03

CANLINSBC_TRXCR_COMP_NORMAL_MODE

#define CANLINSBC_TRXCR_COMP_NORMAL_MODE   0x01

CANLINSBC_TRXCR_COMP_SILENT_MODE

#define CANLINSBC_TRXCR_COMP_SILENT_MODE   0x03

CANLINSBC_TRXCR_COMP_STANDBY_MODE

#define CANLINSBC_TRXCR_COMP_STANDBY_MODE   0x00

CANLINSBC_TRXCR_CPNE

#define CANLINSBC_TRXCR_CPNE   0x10

CANLINSBC_TRXCR_PNCFOK

#define CANLINSBC_TRXCR_PNCFOK   0x20

CANLINSBC_TX_DRV_BUFFER_SIZE

#define CANLINSBC_TX_DRV_BUFFER_SIZE   100

CAN-LIN SBC driver buffer size.

Specified size of driver ring buffer.

Note

Increase buffer size if needed.

CANLINSBC_WDCR1_WDC_MASK

#define CANLINSBC_WDCR1_WDC_MASK   0xE0

CANLINSBC_WDCR1_WDC_OFF_MODE

#define CANLINSBC_WDCR1_WDC_OFF_MODE   0x20

CAN-LIN SBC Watchdog Configuration Register 1 (WDCR1) setting.

Specified setting for Watchdog Configuration Register 1 (WDCR1) of CAN-LIN SBC Click driver.

CANLINSBC_WDCR1_WDC_TIME_OUT_MODE

#define CANLINSBC_WDCR1_WDC_TIME_OUT_MODE   0x40

CANLINSBC_WDCR1_WDC_WINDOW_MODE

#define CANLINSBC_WDCR1_WDC_WINDOW_MODE   0x80

CANLINSBC_WDCR1_WDLSP

#define CANLINSBC_WDCR1_WDLSP   0x04

CANLINSBC_WDCR1_WDLW

#define CANLINSBC_WDCR1_WDLW   0x02

CANLINSBC_WDCR1_WDPRE_FACTOR_1

#define CANLINSBC_WDCR1_WDPRE_FACTOR_1   0x00

CANLINSBC_WDCR1_WDPRE_FACTOR_1_5

#define CANLINSBC_WDCR1_WDPRE_FACTOR_1_5   0x08

CANLINSBC_WDCR1_WDPRE_FACTOR_2_5

#define CANLINSBC_WDCR1_WDPRE_FACTOR_2_5   0x10

CANLINSBC_WDCR1_WDPRE_FACTOR_3_5

#define CANLINSBC_WDCR1_WDPRE_FACTOR_3_5   0x18

CANLINSBC_WDCR1_WDPRE_MASK

#define CANLINSBC_WDCR1_WDPRE_MASK   0x18

CANLINSBC_WDTRIG_RESET

#define CANLINSBC_WDTRIG_RESET   0x55

CAN-LIN SBC Watchdog Trigger Register (WDTRIG) setting.

Specified setting for Watchdog Trigger Register (WDTRIG) of CAN-LIN SBC Click driver.